The present invention relates to Electrical Over-Stress (EOS) and Electrostatic Discharge (ESD) protection in high density integrated circuits.
Modern integrated circuits are easily damaged by excess voltages, and one common source of such potentially damaging voltages is caused when two materials are rubbed together. A person can develop very high static voltage, from a few hundred to several thousand volts, simply by walking across a room or by removing an IC from its plastic package, even when careful handling procedures are followed. The impact of ESD damage due to handling and testing can have a significant influence on product yield. Large ICs manufactured in advanced processes may only have 30 to 40 chips per six inch wafer. Any product loss due to ESD damage has a direct impact on profitability and even fall-outs of the order of 1% are not acceptable. Another issue which gives increasing importance to ESD control is the move towards replaceable ICs in electronic systems. Instead of replacing the whole circuit board, as used to be the standard practice, users are now encouraged to purchase upgrades to their microprocessors and memory cards and perform the installation themselves. Since the installation does not necessarily take place in an ESD-safe environment, the ICs need to be ESD robust.
The major source of ESD exposure to ICs is from the human body, and is known as the Human Body Model (HBM) ESD source. A charge of about 0.6 C can be induced on a body capacitance of 150 pF, leading to electrostatic potentials of 4 kV or greater. Any contact by a charged human body with a grounded object, such as the pin of an IC, can result in a discharge for about 100 ns with peak currents of several amperes to the IC.
A second source of ESD is from metallic objects, and is known as the machine model (MM) ESD source. The MM ESD source is characterized by a greater capacitance and lower internal resistance than the HBM ESD source. The MM ESD model can result in ESD transients with significantly higher rise times than the HBM ESD source.
A third ESD model is the charged device model (CDM). Unlike the HBM ESD source and the MM ESD source, the CDM ESD source includes situations where the IC itself becomes charged and discharges to ground. Thus, the ESD discharge current flows in the opposite direction in the IC than that of the HBM ESD source and the MM ESD source. CDM pulses also have very fast rise times compared to the HBM ESD source.
A longstanding problem is that if such a high voltage is accidentally applied to the pins of an IC package, the discharge can cause gate oxide breakdown of the devices to which it is applied. The breakdown may cause immediate destruction of the device, or it may weaken the oxide enough such that failure may occur early in the operating life of the device and thereby cause later device failure in the field.
In MOS integrated circuits, the inputs are normally connected to drive the gate of one or more MOS transistors. The term xe2x80x9cMOSxe2x80x9d is used in this application, as is now conventional, to refer to any insulated-gate-field-effect-transistor, or to integrated circuits which include such transistors. Furthermore, all pins are provided with protective circuits to prevent voltages from damaging the MOS gates. These protective circuits, normally placed between the input and output pads on a chip and the transistor gates to which the pads are connected, are designed to begin conducting, or to undergo breakdown, thereby providing an electrical path to ground (or to the power-supply rail) when excess voltage occurs. Such protection devices are designed to avalanche (passing a large amount of current, and dissipating the energy of the incoming transient) before the voltage on the input pin can reach levels which would damage the gate oxide. Since the breakdown mechanism is designed to be nondestructive, the protective circuits provide a normally open path that closes only when the high voltage appears at the input or output terminals, harmlessly discharging the node to which it is connected.
However, technological advances are leading to the creation of smaller and faster components that are increasingly more fragile. The output stages of MOS circuits which, until now, have been capable of withstanding high discharge currents, are becoming more vulnerable. In particular, the advantages of the various techniques for improving the performance characteristics of integrated circuits are offset by increased sensitivity to over-voltages or discharges. Breakdown voltages of the junctions or punch-through voltages between drain and source of the MOS transistors are becoming lower and the gate oxide is more fragile.
ESD protection for MOS output buffers has typically relied on a parasitic lateral bipolar transistor of the MOS devices. When the voltage reaches the breakdown voltage of the devices, the lateral transistors should turn on and clamp the pad voltage at a sufficiently low voltage to protect the output buffer. The devices typically have a snap-back characteristic during breakdown. The transistor triggers at a high voltage and snaps-back to a lower voltage to clamp the pad voltage. However, a portion of the MOS device can trigger and snap-back to a lower voltage and conduct all of the current. When this happens, this part can be destroyed before the voltage rises high enough to trigger the rest of the device. This is especially a problem for devices with low resistance substrates, since the substrate is the base of the parasitic lateral transistors and the base is difficult to forward bias if it is low resistance. Low resistance substrates are desirably used on CMOS circuits to prevent latchup of parasitic SCRs in normal operation, however, this conflicts with the use of SCRs for ESD protection.
As integrated circuits (ICs) become more complicated and, as a result, denser, the metal-oxide-semiconductor (MOS) circuit elements that make up the IC must become smaller. As the size of a MOS circuit element shrinks, its operating voltage also tends to drop. In the past, the standard operating voltage of MOS circuit elements was 5V. Newer designs are using operating voltages in the 2.5 to 3.3 volt range. For compatibility, it is desirable for the newer designs to be able to withstand 5V signals. Unfortunately, technologies developed for 3V operation have thin gate oxides, on the order of 100 angstroms. If a thin oxide device designed for 3V operation were instead operated at 5V, the device would have accelerated wear-out due to reduced gate oxide reliability.
ESD protection circuits using MOS circuit elements must be designed to avoid having the oxides stressed by a 5V bond pad voltage during normal operation. At the same time, the protection circuit must turn-on and provide good ESD protection during ESD stress. One prior art solution uses two gate oxide thicknesses. A thinner oxide is used for the internal functional circuitry and a thicker oxide is used for circuitry connected directly to a bond pad. Unfortunately, this adds process complexity by requiring two gate oxide formations. Thus, there is a need for ESD protection circuitry that will not be stressed during 5V operation and that minimizes process complexity.
Because of the importance of ESD protection, it is desirable to improve and provide alternative ESD protection circuits.
Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following figures and specification.
In general, and in an embodiment of the present invention, an integrated circuit is provided with ESD protection circuitry having shared clamp circuits. The integrated circuit has a semiconductor substrate connected to a bond pad for a reference supply voltage. There is a first bus for a first supply voltage, and a second bus for a second supply voltage, wherein the second supply voltage is higher than the first supply voltage. Internal circuitry is connected between the first bus and semiconductor substrate comprising MOS transistors having gate oxide with a first thickness suitable for the first supply voltage but not for the second supply voltage. There is a plurality of signal bond pads for connecting to a respective plurality of external signals, wherein the external signals are operable at approximately the second supply voltage. Local ESD protection circuitry associated with each signal pad has a respective diode connected between each of the plurality of signal bond pads and the second bus. Shared ESD circuitry is connected between the second bus and the semiconductor substrate. The shared ESD circuitry has at least one parasitic bipolar transistor with an emitter connected to the second bus and a collector connected to the semiconductor substrate with a base connected to a control circuit. The control circuit is operable to turn on the parasitic bipolar transistor in response to an ESD zap applied to any of the plurality of signal bond pads and has a plurality of MOS transistors that each have gate oxide only of the first thickness.
Other embodiments of the present invention will be evident from the description and drawings.